Semiconductor process technology continues to reach lower voltages and deeper sub-micron sizes. As the number of transistors per integrated circuit chip has continued to increase, two critical circuit design issues have been presented. The first design issue is the non-uniformity of process parameters within a single die. The second design issue is the increment in power consumption per die.
In deep sub-micron circuit design, variations due to the non-uniformity of process parameters within a single die cause differences in transistor and interconnect characteristics across the single die. These differences in turn negatively impact the performance of the circuit because they generate deviations in MOSFET (Metal Oxide Semiconductor Field Effect Transistor) drive current. This results in propagation delay distributions of the critical path across a chip.
Furthermore, the distribution of process parameters expands from die to die within a single wafer as well as within a lot. After fabrication, operating variations such as power supply voltage, chip temperature, and across-chip temperature also affect the magnitude of the propagation delay. By combining both operational and process induced variations, the magnitude of the propagation delay fluctuates from eighteen percent (18%) to thirty two percent (32%).
The yield of CMOS (Complimentary Metal Oxide Semiconductor) logic circuits that satisfy a specific performance requirement is significantly influenced by the magnitude of critical path delay deviations due to both operational and intrinsic parameter fluctuations. There are two approaches to compensating for the impact of these parameter fluctuations and achieving a desired yield. The first approach is to reduce the performance by operating at a lower clock frequency. The second approach is to increase the supply voltage.
In many portable computing devices such as MP-3 players and digital cameras, the full processing power of a processor is not required all the time. There are certain times when an operating frequency can be reduced. A lower frequency corresponds to a longer allowable delay. This longer time margin also allows a supply voltage level to be lowered whereas the applied lower voltage increases the propagation delay.
Because power consumption is quadratic with the supply voltage and proportional to operating frequency, reducing both operating frequency and supply voltage allows an excellent energy efficient operation. This technique is referred to as adaptive voltage scaling (AVS). Adaptive voltage scaling decreases power consumption without sacrificing performance provided that the tasks that are performed are finished within an allowed time. From the trade-off between performance and energy consumption, supplying just enough voltage to a system at a given frequency represents its optimum power consumption.
Although the operating frequency limits allowable propagation delay, this delay strongly depends on intrinsic process parameters, supply voltage and junction temperature (referred to by the abbreviation “PVT”). The propagation delay in a MOSFET is proportional to the product of the active resistance of the MOSFET (designated RON) and the load capacitance (designated CL). The resistance RON is given by:
                              R          ON                =                              V            DD                                              β              ⁡                              (                                                      V                    DD                                    -                                      V                    T                                                  )                                      α                                              (        1        )            
where α is the velocity saturation term, β is the process transconductance parameter, VDD is the supply voltage, and VT is the threshold voltage. The load capacitance CL is given by:CL=CD+CG+CW  (2)
where CD is the drain capacitance, CG is the gate capacitance, and CW is the interconnect capacitance.
Process parameters and operating junction temperature are not controllable but the supply voltage is controllable. Therefore, if the supply voltage can be adjusted to guarantee the same propagation delay regardless of the other operating conditions, then various simulations are not needed to assure proper functionality. Instead, only one simulation (i.e., the worst case simulation with a small margin) is needed to guarantee proper operation after fabricating the design.
If a design is fabricated as the best process corner, and is operating at low temperature, it needs to be less than three fourths of the minimum supply voltage required to operate at the worst case simulation. This results in power savings by reducing the power supply voltage with regard to process and temperature.
On the other hand, by dynamically adjusting the supply voltage, an individual die is adjusted to a desirable performance. Typically the supply voltage should be raised for dies that are operating slowly and lowered for dies that are operating quickly. In this manner the yield is dramatically improved by the adaptive voltage scaling (AVS) system.
Typical prior art digital control loop circuits employ direct current (DC) to direct current (DC) switching converter circuits. A DC-to-DC switching converter circuit is a device that converts a first DC voltage to a second DC voltage with very little power loss. A boost converter is one type of DC-to-DC switching converter that receives an input voltage of one polarity and outputs a voltage of the same polarity that is larger than the input voltage. A buck converter is another type of DC-to-DC switching converter that receives an input voltage of one polarity, and outputs a voltage of the same polarity that is smaller than the input voltage.
FIG. 1A shows a block diagram of an embodiment of an exemplary prior art buck converter 100. As shown in FIG. 1A, converter 100 has a power supply circuit 102 that receives a pulse width modulated signal PWS and generates a supply voltage VDD in response to the pulse width modulated signal PWS.
Power supply circuit 102 comprises a DC voltage source 110 and an n-channel MOS transistor 112 that has a source, a drain connected to voltage source 110, and a gate connected to receive the pulse width modulated signal PWS. Power supply circuit 102 also comprises a diode D that has an input connected to ground, and an output connected to the source of transistor 112.
Power supply circuit 102 also comprises an inductor L and a capacitor C that form an LC network. Inductor L has a first end connected to the source of transistor 112, and a second end connected to a supply node NS. Capacitor C has a first end connected to the supply node NS and a second end connected to ground. In addition, a load 114 is connected between the supply node NS and ground.
In operation, the pulse width modulated signal PWS turns transistor 112 on and off, which outputs a pulsed current to the LC network. The LC network averages the pulsed current to generate the supply voltage VDD on the supply node NS. The supply voltage VDD has a value that is approximately equal to the duty cycle of the pulse width modulated signal PWS multiplied times the voltage of voltage source 110. For example, when a fifty percent (50%) duty cycle signal is used with a two volt (2 V) voltage source, a supply voltage VDD of approximately one volt (1 V) results.
Diode D is used to provide a continuous conductive path for inductor L. When transistor 112 turns on, current is driven into inductor L, which stores the energy. When transistor 112 turns off, the stored energy is transferred to capacitor C as the voltage on the input of inductor L drops below ground. When the voltage on the input of inductor L drops below ground, diode D turns on, thereby providing a continuous conductive path.
Referring again to FIG. 1A, converter 100 also comprises a compensation circuit 116 that adjusts the duty cycle of the pulse width modulated signal to maintain a roughly constant supply voltage VDD in response to changes in process, voltage, and temperature (PVT).
As shown in FIG. 1A, compensation circuit 116 comprises an adjuster block 120 that divides down (or gains up) the supply voltage VDD on the supply node NS to output an adjusted voltage VA. In addition, compensation circuit 116 comprises an error block 122 that compares the adjusted voltage VA to a band gap reference voltage VBG to generate an error voltage VER.
Compensation circuit 116 further comprises a proportional integrator differentiator (PID) 124 that responds to changes in the error voltage VER, and outputs a control voltage VC in response thereto, and a pulse width modulator 126 that outputs the pulse width modulated signal PWS.
The LC network is a two pole resonant system that stores energy. As a result, any transient introduced to the system, such as a start up transient or a load transient, causes a disturbance. The disturbance causes a response through the LC network that produces an oscillation or a ringing effect.
PID 124 eliminates the ringing effect by providing a zero that cancels one of the poles in the LC network. Canceling one of the poles, in turn, results in a first order system that is inherently stable. In this manner PID 214 converts the second order response of the LC network to a first order response.
Pulse width modulator 126 varies the positive widths (duty cycles) of the pulses in the pulse width modulated signal PWS in response to the control voltage VC output by PID 214. For example, a centered control voltage produces a pulse width modulated signal PWS with a fifty percent (50%) duty cycle. In addition, a driver block 128 drives the pulse width modulated signal PWS onto the gate of transistor 112.
In operation, the band gap reference voltage VBG is generated by a band gap circuit, and is roughly constant over changes in process, voltage, and temperature (PVT). Under normal operating conditions, the adjusted voltage VA and the band gap reference voltage VBG are equal and the error voltage VER is zero. A zero error voltage produces a control voltage VC that, in turn, produces a pulse width modulated signal PWS.
When the adjusted voltage VA varies due to changes in PVT, error block 122 outputs the error voltage VER with a non-zero value. PID 124 filters the error voltage VER to output a control voltage VC. Pulse width modulator 126 responds to the control voltage VC by varying the duty cycle of the pulse width modulated signal PWS which, in turn, changes the supply voltage VDD. This process continues until the adjusted voltage VA and the band gap voltage VBG are again equal.
Thus, compensation circuit 116 adjusts the duty cycle of the pulse width modulated signal PWS to maintain a roughly constant supply voltage VDD in response to changes in process, voltage, and temperature (PVT).
One drawback of switching converter 100 is that diode D introduces an undesirable resistance. One approach to reducing the resistance introduced by diode D is to use a synchronous rectifier. FIG. 1B shows a block diagram that illustrates a typical prior art synchronous rectifier 150.
As shown in FIG. 1B, synchronous rectifier 150 comprises a PMOS driver transistor 152 that has a source connected to a supply voltage VDD, a drain connected to inductor L through an inductor node NL, and a gate. Synchronous rectifier 150 also comprises a NMOS driver transistor 154 that has a source connected to ground, a drain connected to inductor L through the inductor node NL, and a gate.
As also shown in FIG. 1B, synchronous rectifier 150 also comprises a gate signal generator 156 that receives a pulse width modulated signal PWS, and outputs non-overlapping gate signals G1 and G2 to PMOS transistor 152 and NMOS transistor 154, respectively.
In operation, when the pulse width modulated signal PWS transitions low, generator 156 turns off NMOS transistor 154 via gate signal G2, and then turns on PMOS transistor 152 via gate signal G1. When PMOS transistor 152 turns on, transistor 152 sources current into inductor node NL.
When the pulse width modulated signal PWS transitions high, generator 156 turns off PMOS transistor 152 via gate signal G1, and then turns on NMOS transistor 154 via gate signal G2. When NMOS transistor 154 turns on, transistor 154 provides a path to ground to provide a continuous conductive path at the inductor node NL for an inductor.
Another drawback of switching converter 100 is that the converter requires a band gap reference voltage source to respond to changes in PVT. A band gap reference voltage source, however, is a complex circuit that provides only a roughly constant voltage over changes in PVT.
A further drawback of switching converter 100 is that switching converter 100 requires a proportional integrator differentiator (PID), which is also a complex circuit, in order to compensate for the second order effects of the LC network. The implementation of a PID circuit adds a heavy hardware burden because a PID control law is typically expressed as a current and prior values of duty ratio, and error, and includes coefficients that require evaluation using multiplication.
In view of the disadvantages inherent in the prior art switching converter circuitry, it would be advantageous to have an improved system and method for compensating for the impact of operational and intrinsic parameter fluctuations on circuit performance by adaptively adjusting the supply voltage to guarantee proper operation of digital processors. It would be advantageous to have an improved system and method for providing a DC-to-DC switching converter that provides a substantially constant supply voltage over changes in PVT without employing a band gap reference voltage source and without employing a PID circuit.
It would also be advantageous to have an improved system and method for digitally self-adjusting a minimum power supply system to regulate a power supply voltage to a minimum value required to operate at a given PVT and a given frequency.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as future uses, of such defined words and phrases.